Method of fabricating a high-voltage transistor
US6509220B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 2, 2002 |
| Grant date | Jan 21, 2003 |
| Priority date | — |
| Expiry date | Jun 14, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making a high voltage insulated gate field-effect transistor with one or more JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first epitaxial layer of a second conductivity type so as to form a first plurality of buried layers disposed at a different vertical depths. A second epitaxial layer is formed on the first epitaxial layer and the implant process repeated to form a second plurality of buried layers in stacked parallel relationship to the first plurality of buried layers. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.