Semiconductor device and alignment method
US6509247B2 · kind B2 · utility
9Cited by
11References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2001 |
| Grant date | Jan 21, 2003 |
| Priority date | — |
| Expiry date | Jan 25, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/975
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A semiconductor wafer (101) includes a first semiconductor die (103) having a first alignment mark (165) disposed in an alignment region (163) to align the first semiconductor die on the wafer. A second semiconductor die (181) has a second alignment mark (167) disposed in the alignment region such that the second alignment mark overlaps the first alignment mark. The area occupied by the overlapping alignment marks is shared between the first and second semiconductor dice to reduce the area and the cost of each die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.