Logical circuit
US6509761B2 · kind B2 · utility
6Cited by
5References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 13, 2001 |
| Grant date | Jan 21, 2003 |
| Priority date | — |
| Expiry date | Nov 13, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Very high speed operation and reduction of power consumption are realized simultaneously in a two-wire type logical circuit having a halt value and an effective value as signal values. Signal rise transition delay time and signal fall transition delay time are purposely designed asymmetrically and an effective value propagation delay is shortened, thereby accelerating an operating speed of the logical circuit. By eliminating a clock signal from a DOMINO circuit, power consumption is reduced. An architecture for concealing a halt value propagation delay is employed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.