DLL circuit, semiconductor device using the same and delay control method
US6509776B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2001 |
| Grant date | Jan 21, 2003 |
| Priority date | — |
| Expiry date | Apr 6, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A DLL (delay locked loop) circuit includes a signal propagation system and a delay control system. The signal propagation system includes a delay circuit which delays a reference clock signal based on a delay control signal to generate a delayed clock signal. The delay control system includes a sampling circuit, a phase comparing circuit and a delay control circuit. The sampling circuit outputs a first clock signal having a pulse corresponding to one of n (n is an integer more than 1) pulses of the delayed clock signal. The phase comparing circuit compares the first clock signal as a first comparison input signal and the reference clock signal as a second comparison input signal in phase to output a phase difference. The delay control circuit generates the delay control signal based on the phase difference from the phase comparing circuit to output to the delay circuit of the signal propagation system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.