Method and apparatus for reducing DC offset
US6509777B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2001 |
| Grant date | Jan 21, 2003 |
| Priority date | — |
| Expiry date | Jan 23, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/30
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various circuits and methods provide for dc offset reduction that is effective under varying circuit and signal conditions. The offset signal is first sampled and stored, and then subtracted from the signal path via a programmable transconductance amplifier that is placed in a feedback loop during offset reduction. By designing the transconductance amplifier to have programmable gain, the offset reduction technique is capable of compensating for variations in the magnitude of the offset signal. In one embodiment, an amplifier is placed in the feedback path in series with the programmable transconductance amplifier to optimize the trade off between noise and accuracy of offset reduction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.