High-speed CMOS buffer circuit with programmable quadratic transfer function
US6510012B1 · kind B1 · utility
6Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2000 |
| Grant date | Jan 21, 2003 |
| Priority date | — |
| Expiry date | Sep 10, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45626
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An asymmetry correction circuit for correcting an asymmetry signal includes a first transconductance circuit for transforming the asymmetry signal to a bias current in a first current path, a second transconductance circuit to form the bias current in a second current path, and a feed-forward circuit for transforming the asymmetry signal to a positive difference current and a negative difference current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.