Semiconductor memory device
US6510087B2 · kind B2 · utility
6Cited by
5References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2001 |
| Grant date | Jan 21, 2003 |
| Priority date | — |
| Expiry date | Sep 25, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2281
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device comprises a memory cell array, a first latch circuit group, and a second latch circuit group. The first latch circuit group sequentially outputs n/2 bit read data of n-bit read data from the memory cell array in response to sequentially shifted read control signals. The second latch circuit group sequentially outputs the remaining n/2 bit read data in response to the sequentially shifted read control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.