DRAM interface circuit providing continuous access across row boundaries
US6510097B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 2, 2001 |
| Grant date | Jan 21, 2003 |
| Priority date | — |
| Expiry date | Nov 2, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interface circuit controls access to a dynamic random-access memory having multiple banks, each bank having multiple rows of memory cells, according to received address signals. The address signals are decoded in such a way that when access to a consecutive series of addresses crosses from a first row to a second row, these two rows are always disposed in separate banks. The second row is activated during access to the first row, and the first row is precharged during access to the second row, enabling access to proceed without interruption across the row boundary. In particular, burst access can proceed from row to row continuously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.