Method and apparatus for transferring data in a dual port memory
US6510098B1 · kind B1 · utility
414Cited by
5References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 28, 1997 |
| Grant date | Jan 21, 2003 |
| Priority date | — |
| Expiry date | May 28, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system 20 includes a first array 100 and a second array 102 of memory cells. The memory system allows for a quick transfer of the contents of one of the arrays with another one of the arrays. Through the use of a transfer gate (128) interposed between column decoders (150 and 152) corresponding to the two memory arrays, data may be transferred between the two arrays in a single timing cycle. Furthermore, even given the interconnection between the two memory arrays due to the transfer gate, the two memory arrays can be operated independently of one another, with respect to address, data, and timing information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.