Memory control with dynamic driver disabling
US6510099B1 · kind B1 · utility
27Cited by
4References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2001 |
| Grant date | Jan 21, 2003 |
| Priority date | — |
| Expiry date | Sep 28, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
It is determined whether one or more memory devices coupled with each output of one or more output buffers by a terminated bus are in a first power state or a second power state. Each output buffer has a first impedance state and a second impedance state. The one or more output buffers are placed or maintained in the first impedance state in response to determining each of the one or more memory devices is in the first power state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.