Method and apparatus combining a plurality of virtual circuits into a combined virtual circuit
US6510158B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1999 |
| Grant date | Jan 21, 2003 |
| Priority date | — |
| Expiry date | Apr 30, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and apparatus includes processing for combining a plurality of virtual circuits into a combined virtual circuit, where such processing begins by buffering cells of each virtual circuit into a corresponding buffer. The processing then continues by obtaining priority information for each virtual circuit and obtaining logical buffer de-queuing information. The priority information, for example, may equate to priorities established via the varying levels of ATM services. The logical buffer de-queuing information corresponds to an access sequence for a plurality of logical ring buffers that are comprised of the buffers, or buffer identifiers. The processing then continues by generating the combined virtual circuit based on the logical buffer de-queuing information and the priority information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.