Circuit, architecture and method for reading an address counter and/or matching a bus width through one or more synchronous ports
US6510483B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2000 |
| Grant date | Jan 21, 2003 |
| Priority date | — |
| Expiry date | Mar 21, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/108
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to select (i) a read-back address signal or (ii) a data signal as an output signal in response to one or more first control signals. The second circuit may be configured to generate (i) the read-back address signal and (ii) a cycle identification signal in response to an internal address signal and one or more second control signals. The third circuit may be configured to generate one or more I/O control signals in response to the cycle identification signal, where the one or more I/O control signals may determine the format of the output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.