Method and apparatus for high-speed network rule processing
US6510509B1 · kind B1 · utility
105Cited by
4References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 29, 1999 |
| Grant date | Jan 21, 2003 |
| Priority date | — |
| Expiry date | Mar 29, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/12
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A high-speed rule processing apparatus is disclosed that may be used to implement a wide variety of rule processing tasks such as network address translation, firewall protection, quality of service, IP routing, and/or load balancing. The high-speed rule processor uses an array of compare engines that operate in parallel. Each compare engine includes memory for storing instructions and operands, an arithmetic-logic for performing comparisons, and control circuitry for interpreting the instructions and operands. The results from the array of compare engines is prioritized using a priority encoding system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.