Balanced cryptographic computational method and apparatus for leak minimizational in smartcards and other cryptosystems
US6510518B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 1999 |
| Grant date | Jan 21, 2003 |
| Priority date | — |
| Expiry date | Jun 3, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/122
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Cryptographic devices that leak information about their secrets through externally monitorable characteristics (such as electromagnetic radiation and power consumption) may be vulnerable to attack, and previously-known methods that could address such leaking are inappropriate for smartcards and many other cryptographic applications. Methods and apparatuses are disclosed for performing computations in which the representation of data, the number of system state transitions at each computational step, and the Hamming weights of all operands are independent of computation inputs, intermediate values, or results. Exemplary embodiments implemented using conventional (leaky) hardware elements (such as electronic components, logic gates, etc.) as well as software executing on conventional (leaky) microprocessors are described. Smartcards and other tamper-resistant devices of the invention provide greatly improved resistance to cryptographic attacks involving external monitoring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.