Method for improving personal computer reliability for systems that use certain power saving schemes
US6510528B1 · kind B1 · utility
22Cited by
15References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 14, 1999 |
| Grant date | Jan 21, 2003 |
| Priority date | — |
| Expiry date | Dec 14, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/106
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A periodic system “wake-up” is implemented during S1, S2 or S3 states utilizing a hardware timer. A memory scrubbing routine is initiated that reads out all memory locations and writes back any memory locations that have single bit (correctable) Error Correction Code errors. This procedure minimizes the chances of a multiple bit error build up over time that may cause an unrecoverable error. The scrubbing routine is invoked whenever the system is brought out of S1, S2, or S3 state to insure that there are no single bit errors present when full system operation is resumed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.