Method for manufacturing trench-gate type power semiconductor device
US6511886B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 26, 2001 |
| Grant date | Jan 28, 2003 |
| Priority date | — |
| Expiry date | Dec 26, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
Abstract
A method for manufacturing a trench-gate type power semiconductor device is provided. A drift region having a low concentration of a first conductivity type and a body region of a second conductivity type are formed on a semiconductor substrate having a high concentration of the first conductivity type. A trench is formed using a nitride layer pattern and a sidewall oxide layer formed at sidewalls of the nitride layer pattern as a mask, and then the sidewall oxide layer is removed. The corners of the trench are rounded by performing a heat treatment in a hydrogen atmosphere. A source region having a high concentration of the first conductivity type is formed using the nitride layer pattern as a mask. The nitride layer pattern is removed, and an upper oxide layer pattern is formed to cover a predetermined portion of the source region and the gate conductive layer. A body contact region of the second conductivity type is formed using the upper oxide layer pattern as a mask. A source electrode is formed to be electrically connected to the body contact region, and a drain electrode is formed to be electrically connected to the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.