Thin film transistor substrate and process for producing the same
US6512270B2 · kind B2 · utility
2Cited by
2References
3Claims
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Key dates
| Filing date | Aug 20, 2001 |
| Grant date | Jan 28, 2003 |
| Priority date | — |
| Expiry date | Aug 20, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/441
Abstract
A polycrystalline Si thin film transistor substrate having a self-aligned LDD and provided with a gate made of a Mo—W alloy having a W concentration not lower than 5% by weight and lower than 25% by weight and preferably a W concentration of 17 to 22% by weight, which is formed by a process comprising a wet-etching step using an etching solution having a phosphoric acid concentration of 60% to 70% by weight, has uniform characteristic properties and is excellent in productivity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.