Single structure all-direction ESD protection for integrated circuits
US6512662B1 · kind B1 · utility
53Cited by
20References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 30, 1999 |
| Grant date | Jan 28, 2003 |
| Priority date | — |
| Expiry date | Nov 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/601
Abstract
An overvoltage/overcurrent electrostatic discharge protection single circuit structure for Integrated Circuits protects on all paths and polarities between In/Out, Supply, and Ground pins. The structure is built on the chip substrate with an N well with three P Diffusions therein each containing N+ and P+ diffusions therein to form 6 transistors and 8 parasitic resistors to yield 5 thyristors. The structure provides very fast, symmetrical, full protection while using minimal chip area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.