Apparatus and method for multiple serial data synchronization using channel-lock FIFO buffers optimized for jitter
US6512804B1 · kind B1 · utility
55Cited by
14References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 7, 1999 |
| Grant date | Jan 28, 2003 |
| Priority date | — |
| Expiry date | Apr 7, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S370/907
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The invention provides an apparatus, and related method, for receiving and synchronizing parallel data transmitted over multiple serial data channels. The synchronization technique uses a channel lock FIFO buffer on each received serial data channel. The FIFO buffers are configured to tolerate a significant amount of jitter between channels and clock tree delay within the synchronization apparatus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.