Multi-channel master/slave interprocessor protocol
US6513070B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 1999 |
| Grant date | Jan 28, 2003 |
| Priority date | — |
| Expiry date | Jul 21, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and configuration for interprocessor communication provides reduced latency and complexity, as well as the ability to simultaneously transfer different types of data. A multi-channel interface is disposed between a slave processor and a master processor, wherein the multi-channel interface has a low-latency channel for transferring low-latency information and a high-throughput channel for transferring high-throughput information. The master processor interrupts the slave processor when the master processor has control information to transfer to the slave processor. Interrupt driven notification and the multi-channel interface provide reliable, high-speed communication between dissimilar processors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.