Hierarchical bus arbitration
US6513083B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 1999 |
| Grant date | Jan 28, 2003 |
| Priority date | — |
| Expiry date | Sep 29, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/362
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus allowing two independent arbiters which do not directly talk to one another to function on a common system bus, allowing efficient operation of a master controller, and virtually endless capability to add peripherals to the common system bus without problems or major modifications commonly associated with additional arbitration overhead. A master controller sets time slot parameters for an external, subordinate arbiter as often as desired. Based on the time slot parameter information, the subordinate arbiter functions on an electrically separated portion of the common system bus during all times but for a time slot associated with communication of the super arbiter over the entire common system bus. During this time, a tri-state buffer element allows communication between portions of the common system bus. In an adaptive arbitration mode, the subordinate arbiter combines static time slot information assigned in configuration registers together with actual bus requests to generate grant signals to the requesting devices, and reassigns all or portions of time slots which, although assigned to a particular device, are left unused for the relevant system cycle. A…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.