Communications receiver arrangement
US6513136B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 2, 1999 |
| Grant date | Jan 28, 2003 |
| Priority date | — |
| Expiry date | Nov 2, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0057
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver in a digital communications system, in which the digital data occupy a number of levels, equalises the erroneous-count rates for the various data levels by deriving the count rates for the levels, comparing these count rates with each other and using the comparison result to adjust the threshold level which is used to detect the received data train. The error-counts are preferably derived as a byproduct of a Forward Error Correction system already available for performing normal error correction on the received data. The receiver arrangement is envisaged to find predominant application in a two-level system involving logical “1”'s and “0”'s, though it is applicable also to systems with three or more levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.