Insulated-gate field-effect semiconductor device
US6515332B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 16, 2000 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Feb 16, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/258
Abstract
An insulated-gate field-effect semiconductor device, preferably of the SOI type, has source (3) and drain (4) regions in a semiconductor body portion (1) at a first major surface of a semiconductor substrate (10). The gate-terminal metallisation (25) is present at an opposite second major surface (12) of the substrate (10). A gate connection (15,55) is present between the gate electrode (5) and the substrate (10) to connect the gate electrode (5) to the gate-terminal metallisation (25). This arrangement permits better use of the layout area for source-terminal and drain-terminal metallisations, and their connections, at the upper major surface (11) of the body portion (1), without introducing an on-resistance penalty. The part of the gate connection provided by the substrate (10) does not increase the on-resistance of the main current path through the device, i.e. between the source (3) and drain (4). Furthermore, a p-n junction diode can be readily integrated between the channel region (2) and the gate connection (15,55).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.