Sigma delta modulator with buried data
US6515603B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 26, 2000 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Jun 26, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/3015
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A sigma delta modulator is disclosed and claimed. In one embodiment, the sigma delta modulator may comprise input means for inputting an input signal stream; summing means interconnect to the input means for adding a feedback signal stream to the input signal to produce an altered input signal stream; low pass filtering means interconnected to the summing means for low pass filtering the altered input signal stream to produce a low pass filtered signal stream; bit stuffing means for adding predetermined values in predetermined positions in the low pass filtered signal stream to form a bit stuffed low pass filtered stream; and a quantizer for quantizing the bit stuff low pass filtered signal to produce an output signal stream, the output signal stream also being fed back to the summing means so as to form the feedback signal stream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.