Non-volatile memory cell with enhanced cell drive current
US6515899B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2001 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Nov 9, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0433
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory cell is disclosed with increased drive current. A low voltage read transistor is used to increase the drive current. However, with a low voltage read transistor, extra protection is needed to ensure the read transistor is not damaged by high voltage. In one aspect, an isolation transistor is inserted between the read transistor and a sense transistor. The isolation transistor, read transistor and sense transistor are connected in series. When a high voltage is used during an erase operation of the memory cell, the isolation transistor absorbs some of the voltage to protect the read transistor from an excessive voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.