Nonvolatile semiconductor memory device having reduced erase time and method of erasing data of the same
US6515908B2 · kind B2 · utility
22Cited by
4References
17Claims
0Family size
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Key dates
| Filing date | May 1, 2001 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | May 1, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3445
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Erasing is performed two times for narrowing a distribution width of threshold voltages of memory cells, and reducing the number of memory transistors to be subjected to over-erase verify. The erase verify voltage for the first erasing is set more strictly than the erase verify voltage for the second erasing. The erase pulses for the second erasing can be reduced in number, and the erasing time can be further reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.