Partial refresh feature in pseudo SRAM
US6515929B1 · kind B1 · utility
14Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2002 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Jan 16, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pseudo SRAM integrated circuit device is achieved. The device comprises, first, a memory array comprising a plurality of dynamic storage cells. Finally, an access controller is included. The access controller provides read and write access to the memory array from an external device. The access controller performance is compatible with a standard SRAM memory device. The access controller enables a partial data retention mode comprising selective refreshing of at least one part of the memory array and non-refreshing of at least one other part of the memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.