Method and apparatus for reducing average power in memory arrays by switching a diode in or out of the ground path
US6515935B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 19, 2001 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Oct 19, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4074
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for reducing power in SRAMS and DRAMS is implemented by dynamically controlling a voltage applied to individual memory sections of a semiconductor memory array. Individual sections of memory are isolated from a fixed power supply by inserting one or more NFETs and diodes between GND and a negative connection of an individual memory section. The voltage applied to each memory section is controlled by applying a separate variable voltage to each gate of all NFETs connected to a particular memory section. If a memory section is not accessed, the voltage to that section can be lowered, saving power. If a memory section is accessed, the voltage to that section may be raised, providing more power and shortening read and write times.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.