Self-adjusting clock phase controlled architecture
US6516006B1 · kind B1 · utility
4Cited by
16References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 16, 1999 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Feb 16, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A self-adjusting path is created by utilizing a phase detector and modifying a clock path and a data path to enable the passing of data in either phase of the clock. The new input path is controlled by the output of the phase detector. Each time a command is issued, the phase of the clock is detected and latched. The phase of the clock at the time the command issues is thus captured and can propagate through the pipeline along with the data. Accordingly, each stage along the data path can be synchronized to a different phase of the clock to reduce data corruption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.