Interconnection process and interface using parallelized high-speed serial links
US6516040B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 1999 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Aug 13, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J2203/0089
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A process and interface for interconnection of multiprocessor modules by point-to-point serial-to-parallel links. Data processing or data communication modules (A and B) are interconnected by means of high-speed point-to-point serial links conveying multiplexed information organized into frames comprising a start-of-frame recognition pattern. The process, on transmission and on reception, performs an analog synchronization of the basic clocks of the modules to a reference clock generated by one of the modules designated as a reference module, called the master module, the other modules being called slave modules, and a digital synchronization of the start-of-frame of each slave module to the start-of-frame sent by the master module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.