Echo canceller having improved non-linear processor
US6516063B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2000 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Mar 24, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04M9/082
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A non-linear processor for use in an echo canceller is set forth. The non-linear processor includes a center clipping digital filter receiving an echo compensated signal. The non-linear processor provides a center clipped output signal having non-linear thresholds at values of +TNLP and −TNLP. The value of TNLP is dynamically dependent, at least in part, on echo return loss measurements. To limit the processor's susceptibility to corruption from double-talk conditions, the non-linear processor inhibits the dynamic setting of the TNLP value when a double-talk condition is present. Additionally, or in the alternative, the non-linear processor locks the value of the echo return loss measurement after a predetermined number of consecutive echo return loss measurements have values falling within a predetermined range of one another. Such locking further reduces the susceptibility of the non-linear processor to corruption from double-talk conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.