Block level analysis of segmentation tags
US6516091B1 · kind B1 · utility
15Cited by
13References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 9, 1999 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Sep 9, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N1/40062
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A system for processing segmentation tags to generate a block level tag representative of a group of segmentation tags. The system includes first and second statistic compilation circuits, each of the compilation circuits being connected to receive segmentation tags and compile a statistic for a plurality of the received segmentation tags. An address controller connected to the first and second statistic compilation circuits operates to select one of the first and second compilation circuits to receive the segmentation tags.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.