Circuit arrangement with combinatorial blocks arranged between registers
US6516334B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 19, 1997 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Apr 27, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3869
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In the circuit arrangement, combinatorial blocks are arranged between an input register (RG1) and an output register (RG2). The output of the input register (before the combinatorial blocks (KBL)) is connected to an analysis unit (ANA) that analyzes the value (EW) of the output of the input register (RG1) and send an enable signal (EN) to the output register (RG2) (after the combinatorial blocks) when the output value (AW) of the combinatorial blocks (KBL) must be present after the value (EW) of the output of the input register (RG1). The transit time required for an operation in the circuit arrangement can thus be shortened given certain value combinations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.