Method and apparatus for transaction pacing to reduce destructive interference between successive transactions in a distributed symmetric multiprocessor system
US6516379B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 1999 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Nov 8, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based ache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. Since the achievement of coherency is distributed in time and space, the node controller helps to eliminate certain types of snoop collisions by pacing commands selected from its queues in certain circumstances. After a command is selected for snoop from a particular queue, the node controller does not select another command for snoop from that particular queue until the command returns for snoop, at which time the node controller may introduce a configurable delay before allowing a command to be selected from that particular queues.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.