Set-associative cache having a configurable split and unified mode

US6516387B1 · kind B1 · utility

Assignee

• LSI Logic Corporation · US

Inventor

• Stefan Auracher · Baierbrunn, DE

Key dates

• Filing date: Jul 30, 2001
• Grant date: Feb 4, 2003
• Expiry date: Jul 30, 2021

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F12/0864
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A set-associative cache having a selectively configurable split/unified mode. The cache may comprise a memory and control logic. The memory may be configured for storing data buffered by the cache. The control logic may be configured for controlling the writing and reading of data to and from the memory. The control logic may organise the memory as a plurality of storage sets, each set being mapped to a respective plurality of external addresses such that data from any of said respective external addresses maps to that set. The control logic may comprise allocation logic for associating a plurality of ways uniquely with each set, the plurality of ways representing respective plural locations for storing data mapped to that set. In the unified mode, the control logic may assign a first plurality of ways to each set to define a single cache region. In the split mode, the control logic may partition the first plurality of ways to define a first and a second sub-group of ways assigned to each set, to define a respective first and second cache region.