Processor executing unpack instruction to interleave data elements from two packed data
US6516406B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2000 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Sep 8, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49921
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.