Channel interface and protocols for cache coherency in a scalable symmetric multiprocessor system
US6516442B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 1999 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Mar 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17375
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A high-speed point-to-point Channel couples command initiators and memory with the switch matrix and with I/O subsystems. Each end of a channel is connected to a Channel Interface Block (CIB). The CIB presents a logical interface to the Channel, providing a communication path to and from a CIB in another IC. CIB logic presents a similar interface between the CIB and the core-logic and between the CIB and the Channel transceivers. A channel transport protocol is is implemented in the CIB to reliably transfer data from one chip to another in the face of errors and limited buffering.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.