Integrated circuit design correction using fragment correspondence
US6516459B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 10, 2000 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Jul 10, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/36
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Layout correction is accomplished using a forward mapping technique. Forward mapping refers to mapping of fragments from a reticle to a target layout, while backward mapping refers to mapping of fragments from the target layout to the reticle. Forward mapping provides a technique for making an unambiguous mapping for each reticle fragment to a corresponding target layout fragment. The mapping does not necessarily provide a one-to-one correspondence between reticle fragments and target layout fragments. That is, multiple reticle fragments can map to a single target layout fragment. An edge placement error for the target layout fragments is used to make positioning corrections for the corresponding reticle fragment(s). Edge placement error can be determined, for example, with a simulation process that simulates a manufacturing process using the reticles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.