Semiconductor memory device using hemispherical grain silicon for bottom electrodes
US6518612B2 · kind B2 · utility
1Cited by
12References
3Claims
0Family size
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Key dates
| Filing date | Dec 20, 2000 |
| Grant date | Feb 11, 2003 |
| Priority date | — |
| Expiry date | Dec 20, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/905
Abstract
A semiconductor device for use in a memory cell including an active matrix provided with a silicon substrate, at least one transistor formed on the silicon substrate, a number of bottom electrodes formed over the transistors, a plurality of conductive plugs to electrically connect the bottom electrodes to the transistors, respectively, and an insulating layer formed around the conductive plugs. In the device, by carrying out a carbon treatment to top surface portions of the bottom electrode structure, it is possible to secure enough space to prevent the formation of bridges between the bottom electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.