Thin film transistor array substrate for liquid crystal display and method for fabricating same
US6518630B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2001 |
| Grant date | Feb 11, 2003 |
| Priority date | — |
| Expiry date | Nov 19, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A thin film transistor array substrate includes a substrate, a gate wire with a gate line and a gate electrode formed on the substrate, a gate insulating layer covering the gate wire, and a semiconductor pattern formed on the gate insulating layer. A data wire is formed on the gate insulating layer and the semiconductor pattern with a data line, and a source electrode and a drain electrode. The data wire bears a multiple-layered structure having a metallic layer and an intermetallic compound layer. A protective layer is formed on the data wire and the semiconductor pattern. A pixel electrode is formed on the protective layer while contacting the drain electrode through a contact hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.