Capacitive alignment structure and method for chip stacking
US6518679B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2000 |
| Grant date | Feb 11, 2003 |
| Priority date | — |
| Expiry date | May 29, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An alignment structure (14) and method for aligning a first circuit image region (18) of a microelectronic chip (10) with a second circuit region (20) of a wafer (12). The alignment structure comprises a plurality of passive coupling elements (22) attached to the chip and arranged in a linear array and further comprises a plurality of electrodes (24) attached to the wafer and arranged in a linear array. The electrodes are arranged into a set of first driven electrodes (46), a set of second driven electrodes (48) and a set of sensing electrodes (50). The first driven, second driven and sensing electrodes are arranged alternatingly with one another and may each include one or more plates (62). The first and second driven electrodes are driven, respectively, with sine wave signals 180 degrees out of phase with one another. When each passive coupling element is centered over a corresponding sensing electrode, the signals from all of the sensing electrodes are null, indicating that the first circuit image region is aligned with the second circuit image region in the alignment direction. In an alternative embodiment, individual electrodes are configurable into different size first driven…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.