Input/output architecture for efficient configuration of programmable input/output cells
US6518787B1 · kind B1 · utility
105Cited by
17References
25Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 21, 2000 |
| Grant date | Feb 11, 2003 |
| Priority date | — |
| Expiry date | Sep 21, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17744
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable input/output memory architecture. The programmable input/output memory cells are disposed in two segments about the periphery of the chip. Each segment has two data buses for separate reading and writing of the configuration register. Each cell is selected and configured according to user specifications. Corresponding memory cells from each segment share the same select line, therefore two bytes of configuration data are accessed together and the data is propagated through both segments approximately concurrently thereby reducing propagation delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.