Discrete delay line system and method
US6518812B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2000 |
| Grant date | Feb 11, 2003 |
| Priority date | — |
| Expiry date | Jul 20, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/265
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A composite delay line includes a first and a second delay line connected to a multiplexer. The multiplexer has a first and a second input. The first delay line includes an input, an output and first control means for controlling delay. The second delay line includes an input, an output and second control means for controlling delay. The output of each delay line is connected to the input of the multiplexer. Control logic connected to the first control means selects a delay through the first delay line. Control logic connected to the second control means selects a delay through the second delay line. Control logic connected to the multiplexer selects between the output of the first delay line and the second delay line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.