Parallel circuit comprising a plurality of IGBTs
US6518821B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 7, 2001 |
| Grant date | Feb 11, 2003 |
| Priority date | — |
| Expiry date | Sep 7, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a parallel circuit (10) comprising a plurality of high-power IGBTs (T1, . . . ,T3) which are each driven by a dedicated gate drive circuit (GD1,. . . ,GD3), each of the gate drive circuits (GD1,. . . ,GD3) having, at its output, a p-channel MOSFET (M1, M3, M5) and an n-channel MOSFET (M2, M4, M6) in a push-pull arrangement and the outputs of the gate drive circuits (GD1, . . . ,GD3) being connected to the gates of the IGBTs (T1,. . . ,T3) in each case via a gate resistor (R1,. . . ,R3), a parallel circuit comprising more than two gate drive circuits is made possible by virtue of the fact that the outputs of the gate drive circuits (GD1,. . . ,GD3) are interconnected via a connecting line (11), and that the MOSFETs (M1,. . . ,M6) of the gate drive circuits (GD1,. . . ,GD3) are in each case connected to a positive or negative supply terminal (P1, . . . ,P3 or N1, . . . ,N3) via a constant-current source (CS1,. . . ,CS6).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.