Graphics processing system with multiple strip breakers
US6518971B1 · kind B1 · utility
27Cited by
48References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 15, 1999 |
| Grant date | Feb 11, 2003 |
| Priority date | — |
| Expiry date | Jul 15, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2210/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A graphics accelerator having first and second processors includes a first vertex breaker unit coupled to the first processor, and a second vertex breaker unit coupled to the second processor. The first breaker unit divides an incoming polygon strip into a first set of substrips, while the second breaker unit divides the incoming polygon strip into a second set of substrips. The graphics accelerator further includes a bus coupled with the first and second breaker units for transmitting the incoming polygon strip to the first breaker unit and the second breaker unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.