High-speed on-chip windowed centroiding using photodiode-based CMOS imager
US6519371B1 · kind B1 · utility
30Cited by
10References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2000 |
| Grant date | Feb 11, 2003 |
| Priority date | — |
| Expiry date | Oct 2, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/65
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A centroid computation system is disclosed. The system has an imager array, a switching network, computation elements, and a divider circuit. The imager array has columns and rows of pixels. The switching network is adapted to receive pixel signals from the image array. The plurality of computation elements operates to compute inner products for at least x and y centroids. The plurality of computation elements has only passive elements to provide inner products of pixel signals the switching network. The divider circuit is adapted to receive the inner products and compute the x and y centroids.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.