Configuration bits layout
US6519674B1 · kind B1 · utility
93Cited by
16References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2000 |
| Grant date | Feb 11, 2003 |
| Priority date | — |
| Expiry date | Feb 18, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A configuration bit layout for a reconfigurable chip includes address bits stored along with configuration bits. The blocks of data are loaded onto the reconfigurable chip from an external memory and the address information is decoded to load the configuration bits onto the correct locations in the reconfigurable chip. In this way, configuration data need not be stored sequentially in the external memory. Configurations can be allocated into different slices of the reconfigurable chip as well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.