Method and apparatus for dynamic power control of a low power processor
US6519707B2 · kind B2 · utility
32Cited by
6References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2001 |
| Grant date | Feb 11, 2003 |
| Priority date | — |
| Expiry date | Sep 10, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Briefly, in accordance with one embodiment of the invention, a system includes: a processor, a voltage regulator, and a memory. The voltage regulator is coupled to the processor to adjust the operating voltage of the processor. The memory is coupled to the processor by a memory bus. The memory has stored on it processor instructions that, when executed by the processor, result in modification of the operating frequency of the processor and result in adjustment of the operating voltage of the processor, based, at least in part, on dynamic changes in the processing load of the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.