Method and apparatus for controlling the read clock signal rate of a first-in first-out (FIFO) data memory
US6519722B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 22, 2000 |
| Grant date | Feb 11, 2003 |
| Priority date | — |
| Expiry date | Mar 22, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/076
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for controlling the read clock signal rate of a First-In First-Out data memory is provided. A control signal for controlling the read clock signal rate is derived from an error signal, wherein the level of data contained in the FIFO is used to generate the error signal. The control signal includes an integral element, which comprises the error signal, scaled by a first paramater and integrated over time, and a proportional element, which comprises the error signal scaled by a second parameter. In accordance with the invention, at least one of the first and second scaling parameters is varied in accordance with the absolute error signal level. In a preferred embodiment, the or each parameter is varied as an exponential function of the absolute error signal level. This results in the bandwidth of the apparatus varying exponentially with the absolute error signal level. The dynamic or adaptive nature of the bandwidth enables the apparatus to provide an output data stream with relatively low wander or jitter under normal operating conditions while preventing data loss due to FIFO overflow or underflow in extreme operating conditions. The invention has particular …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.