Generating special uncorrectable error codes for failure isolation
US6519736B1 · kind B1 · utility
22Cited by
9References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 30, 1999 |
| Grant date | Feb 11, 2003 |
| Priority date | — |
| Expiry date | Nov 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/19
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Uncorrectable errors are isolated to one component of a computing system comprising a plurality of components. First, upon detection of an uncorrectable error, a special check bit pattern is generated. This check bit pattern is used to indicate the occurrence of an uncorrectable error, as well as the location of the occurrence of the error. Subsequently, the check bit pattern is incorporated into the data word being transmitted, and thus may be used to isolate an uncorrectable error to the exact location of occurrence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.